1. Field of the Invention
The present invention pertains to a method and apparatus for reducing a power consumption of a central processing unit (CPU) of an electronic unit by switching the CPU between a normal operating state and a sleep state, and more particularly, to returning the CPU to the normal operation state at regular intervals when the CPU has been placed into the sleep state, outputting a predetermined clear signal from the CPU to a monitoring circuit so that the monitoring circuit monitors the state of the CPU, and making reference to an input signal to the CPU from electronic equipment connected to the CPU, and a recording medium having a power consumption reduction program recorded thereon.
2. Discussion of Background and Relevant Information
In recent years, electronic devices are being increasingly designed into, for example, vehicles. Certain electrical devices must remain connected to an electrical power supply (e.g. vehicle battery) even when the vehicle is parked. Thus, such electronic devices consume significant amounts of electrical power twenty-four hours a day. As a result, if the vehicle is parked for an extended period of time, the vehicle battery may be prematurely run down (exhausted). Accordingly, it is desirable to reduce the electrical demands (i.e., energy demand) of the electronic devices when the vehicle is parked. One way to reduce the electrical requirements of such an electronic device (unit) is to place the electronic device into a sleep state when the vehicle is parked.
A microcomputer (e.g., an electronic device containing a CPU) can be used to control and/or operate and/or monitor a plurality of functions. Thus, it is desirable to include a monitoring circuit, such as, for example, a watch dog time (or the like) in the electronic device, in order to return the electronic device to its normal operation state when, for example, the vehicle is to be started (or runs), or a vehicle malfunction or unusual event occurs. If the CPU outputs clear signals to the monitoring circuit at predetermined time intervals, the monitoring circuit concludes that the CPU is in a normal operation state. On the other hand, if the monitoring circuit does not receive the clear signal within the predetermined time interval, the monitoring circuit concludes that the CPU has “locked up” or some other problem has occurred, and the monitoring circuit outputs a reset signal to the CPU. Upon receipt of the reset signal, the CPU is initialized and, hopefully, returns to an initial operation state.
When the CPU is placed into the sleep state, the CPU must be returned to its normal operation state at predetermined intervals in order to ensure that the CPU outputs the clear signal for detection by the monitoring circuit. That is, the microcomputer must be constructed so as to prevent the CPU from going into a runaway state.
When a signal is inputted to the CPU, it is necessary for the CPU to immediately perform the required task, even when the CPU is placed in the sleep state. Therefore, it is necessary to determine whether an actuation signal has been inputted to an input port of the CPU. When the CPU is normally placed in the sleep state, the CPU outputs the clear signal according to a procedure shown in a timing chart of FIG. 5, and the flowchart of FIG. 6.
As shown in FIG. 5, after the CPU enters the sleep state, it returns to the normal operation state for a 10 msec period every 30 msec. The CPU outputs the clear signal and makes reference to the input port thereof. Then, the CPU is placed back into to the sleep state (steps S21-S23 of FIG. 6). Thus, the CPU is in the sleep mode for a 20 msec time period of each 30 msec time period, during which time the electrical consumption of the electrical device is reduced.
According to a conventional method for reducing electrical power consumption of the CPU, it is necessary for the CPU to output the clear signal to the monitoring circuit and to make reference to the input port thereof. Thus, it is necessary for the CPU to return to the normal operation state from the sleep state each time the clear signal is outputted to the monitoring circuit, and to make reference to the input port thereof. However, the electrical power consumed by the CPU during the transition from the sleep state to the normal operation state causes the battery to become discharged in a short period of time.
An apparatus for reducing the electrical power consumption of a CPU is disclosed in Japanese Patent Laid-Open Application No. HEI 8-263326. This apparatus has a first abnormality detection circuit that outputs a first abnormality detection signal to detect an abnormality of the CPU at regular time intervals when the CPU is placed in the sleep state, and a second abnormality detection circuit that outputs a second abnormality detection signal to detect an abnormality of the CPU at regular time intervals when the CPU is in the normal operating state. The time period required to output the second abnormality detection signal is set to be shorter than the time period required to output the first abnormality detection signal, in order to reduce the electrical power consumption of the CPU in the sleep state.
A disadvantage of this apparatus is that it requires that the two abnormality detection circuits generate the different period abnormality detection signals in the sleep state and the normal state. Thus, the construction of the monitoring circuit is complicated and expensive. Further, the interval at which the reference is made to the input port of the CPU is long. Thus, the abnormality detection circuits are incapable of making a fast response to the actuation of the electronic equipment, which makes an operator feel uncomfortable.